Contents

REL 531
Contents
Chapter 1 Introduction
- 1 Introduction to the installation and commissioning manual
  - 1.1 About the complete set of manuals for a terminal
  - 1.2 About the installation and commissioning manual
  - 1.3 Intended audience
    - 1.3.1 General
    - 1.3.2 Requirements
  - 1.4 Related documents
  - 1.5 Revision notes
  - 1.6 Acronyms and abbreviations
Chapter 2 Safety information
- 1 Warning signs
- 2 Caution signs
- 3 Note signs
Chapter 3 Overview
- 1 Commissioning and installation overview
Chapter 4 Unpacking and checking the terminal
- 1 Receiving, unpacking and checking
Chapter 5 Installing the terminal
- 1 Overview
- 2 Mounting the terminal
  - 2.1 Mounting in a 19-inch rack
  - 2.2 Mounting in a 19-inch rack with an additional box type RHGS
  - 2.3 Mounting in a flush
  - 2.4 Mounting on a wall
    - 2.4.1 Mounting the terminal on a wall
    - 2.4.2 Preparing a wall mounted terminal for electrical installation
- 3 Making the electrical connections
  - 3.1 Connecting the CT circuits
  - 3.2 Connecting the auxiliary power, VT and signal connectors
  - 3.3 Connecting to protective earth
  - 3.4 Making the screen connection
- 4 Installing the optical fibres
- 5 Installing the serial communication cable for RS485 SPA/IEC
  - 5.1 RS485 serial communication module
  - 5.2 Informative excerpt from EIA Standard RS-485
  - 5.3 Data on RS485 serial communication module cable
- 6 Installing the
Chapter 6 Checking the external circuitry
- 1 Overview
- 2 Checking the CT and VT circuits
- 3 Checking the power supply
- 4 Checking the binary I/O circuits
  - 4.1 Binary input circuits
  - 4.2 Binary output circuits
Chapter 7 Energising the terminal
- 1 Overview
- 2 Energising the terminal
- 3 Checking the self supervision signals
  - 3.1 Reconfiguring the terminal
  - 3.2 Setting the terminal time
  - 3.3 Checking the self supervision function
    - 3.3.1 Navigating the menus
  - 3.4 Self supervision HMI data
Chapter 8 Configuring the 56/64 kbit data communicationmo dules
- 1 Configuring the fibre optical modem
  - 2 Calculation of optical power budget
- 3 Configuring the short range fibre optical modem
- 4 Configuring the short range galvanic modem
- 5 Configure the interface modules for V.36, X.21andRS530
- 6 Configuring the interface modules for G.703codirectional
- 7 Fault tracing
  - 7.0.1 Comfail function
  - 7.0.2 Explanation of contents in column 2 of table 42
- 8 Configuring the transceiver 21-15xx
  - 9 Co-directional operation
  - 10 Contra-directional operation
- 11 Configuring the transceiver 21-16xx
  - 11.1 X.21 operation
  - 11.2 G.703 co-directional operation
Chapter 9 Setting and configuring the terminal
- 1 Overview
- 2 Entering settings through the local HMI
- 3 Configuring the setting restriction of HMI function
- 4 Activating the restriction of setting
  - 4.1 Local HMI
  - 4.2 Serial communication, change of active group
  - 4.3 Serial communication, setting
- 5 Downloading settings and configuration from a PC
  - 5.1 Establishing front port communication
  - 5.2 Establishing rear port communication
    - 5.2.1 Using the SPA/IEC rear port
    - 5.2.2 Using LON rear port
  - 5.3 Downloading the configuration and setting files
Chapter 10 Requirement of trig condition for disturbance report
- 1 Requirement of trig condition for disturbance report
Chapter 11 Establishing connection and verifying the SPA/IEC-communi cation
- 1 Entering settings
  - 1.1 Entering SPA settings
  - 1.2 Entering IEC settings
- 2 Verifying the communication
  - 2.1 Verifying SPA communication
  - 2.2 Verifying IEC communication
- 3 Optical budget calculation for serial communication withSPA/IEC
Chapter 12 Establishing connection and verifying theLON communication
- 1 Reference
  - 1.1 Verification of the optical budget
    - 1.1.1 Optical budget calculation for serialcommunication with LON
Chapter 13 Verifying settings by secondary injection
- 1 Overview
- 2 Preparing for test
  - 2.1 Overview
  - 2.2 Preparing the connection to the test equipment
  - 2.3 Setting the terminal in test mode
  - 2.4 Connecting test equipment to the terminal
  - 2.5 Verifying the connection and the analog inputs
  - 2.6 Releasing the function(s) to be tested
  - 2.7 Checking the disturbance report settings
  - 2.8 Identifying the function to test in thetechnicalreferencemanual
  - 3 Automatic switch onto fault logic (SOTF)
    - 3.1 External activation of SOTF function
    - 3.2 Automatic initiation of SOTF
    - 3.3 Completing the test
  - 4 Autorecloser (AR)
    - 4.1 Preparing
    - 4.2 Checking the AR functionality
    - 4.3 Checking the reclosing condition
      - 4.3.1 Checking the Inhibit signal
      - 4.3.2 Checking the closing onto a fault
      - 4.3.3 Checking the breaker not ready
      - 4.3.4 Checking the synchro-check condition(forthreephasereclosingcycle)
      - 4.3.5 Checking the operation Stand-by and Off
    - 4.4 Testing the multi-breaker arrangement
    - 4.5 Completing the test
  - 5 Binary signal transfer to remote end (RTC12)
  - 6 Breaker failure protection (BFP)
    - 6.1 Verifying the settings
    - 6.2 Verifying the retrip setting
      - 6.2.1 Checking the retrip function with retrip set to off
      - 6.2.2 Checking the retrip function with current check
      - 6.2.3 Checking the retrip function without current check
    - 6.3 Completing the test
  - 7 Broken conductor check (BRC)
    - 7.1 Measuring the operate and time limit of set values
  - 8 Communication channel test logic (CCHT)
    - 8.1 Testing the logic
  - 9 Current circuit supervision (CTSU)
  - 10 Current reversal and weak end infeed logic(ZCAL)
    - 10.1 Current reversal logic
      - 10.1.1 Checking of current reversal
    - 10.2 Weak end infeed logic
      - 10.2.1 WEI logic at permissive schemes
      - 10.2.2 Testing conditions
    - 10.3 Completing the test
  - 11 Current reversal and weak end infeed logic for residual overcurrentprotection(EFCA)
    - 11.1 Testing the current reversal logic
    - 11.2 Testing the weak-end-infeed logic
      - 11.2.1 If setting parameter WEI=Echo
      - 11.2.2 If setting WEI=Trip
    - 11.3 Completing the test
  - 12 Dead line detection (DLD)
  - 13 Time delayed residual overcurrent protection (TEF)
    - 13.1 Checking the operate values of the currentmeasuringelements
  - 14 Distance protection (ZMn)
    - 14.1 Measuring the operate limit of set values
    - 14.2 Measuring the operate time of distance protection zones
    - 14.3 Completing the test
  - 15 Disturbance recorder (DR)
  - 16 Event counter (CN)
  - 17 Event function (EV)
  - 18 Event recorder (ER)
  - 19 Fault locator (FLOC)
    - 19.1 Measuring the operate limit
    - 19.2 Completing the test
  - 20 Four step time delayed directional residual overcurrentprotection(EF4)
    - 20.1 Testing the direction measuring element
    - 20.2 Testing the current step 4.
      - 20.2.1 Testing the setting NonDirNonRestr or Restrained
      - 20.2.2 Testing the setting ForwRelease or ForwRelRestr
      - 20.2.3 Testing the setting RevBlock or RevBlRestr
      - 20.2.4 Testing the characteristic setting 1=NI,2=VI,3=EIor4=LOG
      - 20.2.5 Testing the characteristic setting 0=DEF
    - 20.3 Testing the Blocking at parallel transformer function.
    - 20.4 Testing the current step 1-3
      - 20.4.1 Testing the setting NonDirNonRestr or Restrained
      - 20.4.2 Testing the setting ForwRelease or ForwRelRestr
      - 20.4.3 Testing the setting RevBlock or RevBlRestr
      - 20.4.4 Testing the time setting t1
    - 20.5 Testing the Switch-onto-fault
      - 20.5.1 Testing the switch-onto-fault with setting 1=IN2>and 2=IN4>Res
      - 20.5.2 Testing the switch-onto-fault with setting 2 = IN4>Res
    - 20.6 Completing the test
  - 21 Fuse failure supervision (FUSE)
    - 21.1 Checking that the binary inputs and outputs operateasexpected
    - 21.2 Measuring the operate value for the negativesequencefunction
    - 21.3 Measuring the operate value for the zero sequence function
    - 21.4 Checking the operation of the du/dt, di/dt based function
    - 21.5 Completing the test
  - 22 High speed binary output logic (HSBO)
    - 22.1 HSBO- trip from communication logic
    - 22.2 ZCOM trip schemes
    - 22.3 HSBO- trip from the high-speed function (HS)
    - 22.4 HSBO- trip from the distance protection zone 1 function (ZM1)
    - 22.5 Completing the test
  - 23 High speed protection (HS)
  - 24 Instantaneous nondirectional overcurrent protection(IOC)
    - 24.1 Measuring the operate limit of set values
      - 24.1.1 Phase overcurrent protection
      - 24.1.2 Residual overcurrent protection (non-dir.)
    - 24.2 Completing the test
  - 25 Loss of voltage check (LOV)
    - 25.1 Measuring the operate limit of set values
  - 26 Supervision of AC input quantities (DA)
    - 26.1 Verifying the settings
    - 26.2 Completing the test
  - 27 Supervision of mA input quantities (MI)
    - 27.1 Verifying the settings
    - 27.2 Completing the test
  - 28 Multiple command (CM)
  - 29 Overload supervision (OVLD)
    - 29.1 Measuring the operate and time limit of set values
  - 30 Phase segregated scheme communication logic includingcurrentreversalandweakend infeedlog...
    - 30.1 Testing permissive underreach
    - 30.2 Testing permissive overreach
    - 30.3 Testing blocking scheme
    - 30.4 Checking of unblocking function
    - 30.5 Completing the test
  - 31 Phase selection logic (PHS)
    - 31.1 Measuring the operate limit of set values
  - 32 Pole discordance protection (PD)
  - 33 Pole slip protection (PSP)
    - 33.1 Measuring the operating characteristics
      - 33.1.1 Applying additional settings
      - 33.1.2 Measuring the impedance boundaries
    - 33.2 Testing the pole slip functionality
    - 33.3 Testing the additional functionality
    - 33.4 Completing the test
  - 34 Power swing detection (PSD)
    - 34.1 Testing overview
    - 34.2 Testing the one-of-three-phase operation
    - 34.3 Testing the two-of-three-phase operation
    - 34.4 Testing the tEF timer and functionality
    - 34.5 Testing the tR1 timer
    - 34.6 Testing the tR2 timer
    - 34.7 Testing the block input
    - 34.8 Completing the test
  - 35 Power swing additional logic (PSL)
    - 35.1 Testing the carrier send and trip signals
    - 35.2 Testing the influence of the residual overcurrent protection
    - 35.3 Controlling of the underreaching zone
    - 35.4 Completing the test
  - 36 Pulse counter logic for metering (PC)
  - 37 Radial feeder protection (PAP)
    - 37.1 Testing the fast fault clearance
    - 37.2 Testing the delayed fault clearance
    - 37.3 Completing the test
  - 38 Setting lockout (HMI)
    - 38.1 Verifying the settings
    - 38.2 Completing the test
  - 39 Scheme communication logic(ZCOM)
    - 39.1 Testing permissive underreach
    - 39.2 Testing permissive overreach
    - 39.3 Testing blocking scheme
    - 39.4 Checking of unblocking logic
      - 39.4.1 Command function with continuousunblocking (Unblock=1)
    - 39.5 Completing the test
  - 40 Scheme communication logic for residual overcurrentprotection(EFC)
    - 40.1 Testing the directional comparison logic function
      - 40.1.1 Blocking scheme
      - 40.1.2 Permissive scheme
    - 40.2 Completing the test
  - 41 Sensitive directional residual overcurrent protection (WEF1)
    - 41.1 Measuring the operate and time limit for set values
  - 42 Sensitive directional residual power protection (WEF2)
    - 42.1 Measuring the operate and time limit of set values
  - 43 Four parameter setting groups (GRP)
    - 43.1 Verifying the settings
  - 44 Single command (CD)
  - 45 Stub protection (STUB)
    - 45.1 Measuring the operate limit of set values
  - 46 Synchrocheck and energizing check(SYN)
    - 46.1 Testing the phasing function
      - 46.1.1 Testing the frequency difference
    - 46.2 Testing the synchrocheck
      - 46.2.1
      - 46.2.2 Testing the voltage difference
      - 46.2.3 Testing the phase difference
      - 46.2.4 Testing the frequency difference
      - 46.2.5 Testing the reference voltage
    - 46.3 Testing the energizing check
      - 46.3.1
      - 46.3.2 Testing the dead line live bus (DLLB)
      - 46.3.3 Testing the dead bus live line (DBLL)
      - 46.3.4 Testing both directions (DLLB or DBLL)
      - 46.3.5 Testing the dead bus dead line (DBDL)
    - 46.4 Testing the voltage selection
      - 46.4.1 Testing the voltage selection for single CB arrangements
      - 46.4.2 Testing the voltage selection for 1 1/2circuit breakerdiameter
    - 46.5 Completing the test
  - 47 Thermal phase overload protection (THOL)
    - 47.1 Measuring the operate and time limit of set values
      - 47.1.1 Testing the protection without external temperaturecompensation (NonComp)
  - 48 Definite time nondirectional overcurrent protection(TOC)
    - 48.1 Measuring the operate limit of set values
      - 48.1.1 Time delayed phase overcurrent
      - 48.1.2 Time delayed residual overcurrent (non-dir.)
    - 48.2 Completing the test
  - 49 Time delayed overvoltage protection (TOV)
    - 49.1 Verifying the settings
      - 49.1.1 Time delayed phase overvoltage protection
      - 49.1.2 Time delayed residual overvoltage protection (non-dir.)
    - 49.2 Completing the test
  - 50 Time delayed undervoltage protection
    - 50.1 Verifying the settings
    - 50.2 Completing the test
  - 51 Tripping logic (TR)
    - 51.1 3ph operating mode
    - 51.2 1ph/3ph operating mode
    - 51.3 1ph/2ph/3ph operating mode
    - 51.4 Completing the test
  - 52 Two step time delayed directional phase overcurrentprotection(TOC3)
    - 52.1 Measuring the operate and time limit for set values
      - 52.1.1 Measuring the operate limit of the low stepovercurrentprotection
      - 52.1.2 Measuring the definite time delay of the low set stage
      - 52.1.3 Measuring the inverse time delay of the low set stage
      - 52.1.4 Measuring the operate limit of the high stepovercurrent protection
      - 52.1.5 Measuring the operate limit of the directional lines.
    - 52.2 Completing the test
  - 53 Two step time delayed non-directional phase overcurrentprotection(TOC2)
    - 53.1 Measuring the operate and time limit for set values
      - 53.1.1 Measuring the operate limit of the lowstep overcurrent protection
      - 53.1.2 Measuring the definite time delay of the low set stage
      - 53.1.3 Measuring the inverse time delay of the low set stage
      - 53.1.4 Measuring the operate limit of the high stepovercurrent protection
    - 53.2 Completing the test
  - 54 Low active power protection (LAPP)
    - 54.1 Measuring the operate limit of set values
      - 54.1.1 Low active power in any phase
      - 54.1.2 Dependability test
      - 54.1.3 Security test with respect to directionality
      - 54.1.4 Time delay test
      - 54.1.5 Completing the test
  - 55 Low active and reactiv power protection (LARP)
    - 55.1 Measuring the operate limit of set values
      - 55.1.1 Low active and reactive power in any phase
      - 55.1.2 Dependability test
      - 55.1.3 Security test with respect to directionality
      - 55.1.4 Time delay test
  - 56 High active power protection (HAPP)
    - 56.1 Measuring the operate limit of set values
      - 56.1.1 High active power in any phase
      - 56.1.2 Dependability test
      - 56.1.3 Security test with respect to directionality
      - 56.1.4 Time delay test
  - 57 High active and reactive power protection (HARP)
    - 57.1 Measuring the operate limit of set values
      - 57.1.1 High active and reactive power in any phase
      - 57.1.2 Dependability test
      - 57.1.3 Security test with respect to directionality
      - 57.1.4 Time delay test
  - 58 Sudden change in phase current protection(SCC1)
    - 58.1 Measuring the operate limit of set values
      - 58.1.1 Sudden change in current in any phase
      - 58.1.2 Dependability test
      - 58.1.3 Time delay test
      - 58.1.4 Completing the test
  - 59 Sudden change in residual current protection(SCRC)
    - 59.1 Measuring the operate limit of set values
      - 59.1.1 Sudden change in residual current
      - 59.1.2 Dependability test
      - 59.1.3 Time delay test
      - 59.1.4 Completing the test
  - 60 Sudden change in voltage protection (SCV)
    - 60.1 Measuring the operate limit of set values
      - 60.1.1 Sudden change in voltage in any phase
      - 60.1.2 Dependability test
      - 60.1.3 Time delay test
      - 60.1.4 Completing the test
  - 61 Overvoltage protection (OVP)
    - 61.1 Measuring the operate limit of set values
      - 61.1.1 Overvoltage in any phase
      - 61.1.2 Dependability test
      - 61.1.3 Time delay test
      - 61.1.4 Completing the test
  - 62 Undercurrent protection (UCP)
    - 62.1 Measuring the operate limit of set values
      - 62.1.1 Undercurrent in any phase
      - 62.1.2 Dependbility test
      - 62.1.3 Time delay test
      - 62.1.4 Completing the test
  - 63 Phase overcurrent protection (OCP)
    - 63.1 Measuring the operate limit of set values
      - 63.1.1 Overcurrent in any phase
      - 63.1.2 Dependability test
      - 63.1.3 Time delay test
      - 63.1.4 Completing the test
  - 64 Residual overcurrent protection (ROCP)
    - 64.1 Measuring the operate limit of set values
      - 64.1.1 Residual overcurrent
      - 64.1.2 Dependability test
      - 64.1.3 Time delay test
      - 64.1.4 Completing the test
Chapter 14 Verifying the internal configuration
- 1 Overview
- 2 Testing the interaction of the distance protection
Chapter 15 Testing the protection system
- 1 Overview
- 2 Testing the interaction of the distance protection
Chapter 16 Checking the directionality
- 1 Overview
- 2 Testing the directionality of the distance protection
- 3 Testing the directional residual overcurrent protection
Chapter 17 Fault tracing and repair
- 1 Fault tracing
  - 1.1 Using information on the local HMI
  - 1.2 Using front-connected PC or SMS
- 2 Repair instruction
- 3 Repair support

ABB REL 531 2.5 Installation Manual

ABB REL 531 2.5 Protection Terminal manual cover

Pages 290

Year 2006

Language(s)

of 290

Installation Manual

290 pages

Application Manual

650 pages

Technical Reference Manual

450 pages

ABB REL 531 2.5 Protection Terminal Specification

The ABB REL 531 2.5 Protection Terminal is a sophisticated device designed for the protection, control, and monitoring of electrical power systems. It integrates advanced protection functions with high-speed communication capabilities, ensuring reliable and efficient operation in various applications. The terminal supports a wide range of protection schemes, including overcurrent, distance, and differential protection, making it suitable for use in transmission and distribution networks.

The REL 531 2.5 features a modular design, allowing for flexible configuration and easy adaptation to specific requirements. It is equipped with a powerful microprocessor that enables precise and fast processing of protection algorithms. The device supports multiple communication protocols, including IEC 61850, DNP3, and Modbus, facilitating seamless integration into modern substation automation systems.

The terminal's user interface is designed for ease of use, featuring a large, clear display and intuitive navigation. It provides comprehensive event recording and fault analysis capabilities, aiding in quick diagnosis and resolution of issues. The REL 531 2.5 also includes self-diagnostic functions to ensure continuous and reliable operation.

In terms of hardware, the REL 531 2.5 is built to withstand harsh environmental conditions, with robust construction and compliance with international standards for electromagnetic compatibility and safety. It offers multiple input and output options, including analog and digital signals, to accommodate various system configurations.

Overall, the ABB REL 531 2.5 Protection Terminal is a versatile and reliable solution for enhancing the protection and control of electrical power systems, combining advanced functionality with user-friendly operation and robust performance.