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2.1 Overview
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2.2 Preparing the connection to the test equipment
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2.3 Setting the terminal in test mode
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2.4 Connecting test equipment to the terminal
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2.5 Verifying the connection and the analog inputs
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2.6 Releasing the function(s) to be tested
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2.7 Checking the disturbance report settings
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2.8 Identifying the function to test in thetechnicalreferencemanual
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3 Automatic switch onto fault logic (SOTF)
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4 Autorecloser (AR)
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4.1 Preparing
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4.2 Checking the AR functionality
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4.3 Checking the reclosing condition
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4.3.1 Checking the Inhibit signal
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4.3.2 Checking the closing onto a fault
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4.3.3 Checking the breaker not ready
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4.3.4 Checking the synchro-check condition(forthreephasereclosingcycle)
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4.3.5 Checking the operation Stand-by and Off
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4.4 Testing the multi-breaker arrangement
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4.5 Completing the test
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5 Binary signal transfer to remote end (RTC12)
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6 Breaker failure protection (BFP)
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7 Broken conductor check (BRC)
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8 Communication channel test logic (CCHT)
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9 Current circuit supervision (CTSU)
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10 Current reversal and weak end infeed logic(ZCAL)
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11 Current reversal and weak end infeed logic for residual overcurrentprotection(EFCA)
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12 Dead line detection (DLD)
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13 Time delayed residual overcurrent protection (TEF)
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14 Distance protection (ZMn)
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15 Disturbance recorder (DR)
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16 Event counter (CN)
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17 Event function (EV)
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18 Event recorder (ER)
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19 Fault locator (FLOC)
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20 Four step time delayed directional residual overcurrentprotection(EF4)
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20.1 Testing the direction measuring element
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20.2 Testing the current step 4.
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20.2.1 Testing the setting NonDirNonRestr or Restrained
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20.2.2 Testing the setting ForwRelease or ForwRelRestr
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20.2.3 Testing the setting RevBlock or RevBlRestr
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20.2.4 Testing the characteristic setting 1=NI,2=VI,3=EIor4=LOG
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20.2.5 Testing the characteristic setting 0=DEF
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20.3 Testing the Blocking at parallel transformer function.
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20.4 Testing the current step 1-3
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20.4.1 Testing the setting NonDirNonRestr or Restrained
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20.4.2 Testing the setting ForwRelease or ForwRelRestr
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20.4.3 Testing the setting RevBlock or RevBlRestr
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20.4.4 Testing the time setting t1
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20.5 Testing the Switch-onto-fault
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20.6 Completing the test
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21 Fuse failure supervision (FUSE)
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21.1 Checking that the binary inputs and outputs operateasexpected
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21.2 Measuring the operate value for the negativesequencefunction
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21.3 Measuring the operate value for the zero sequence function
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21.4 Checking the operation of the du/dt, di/dt based function
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21.5 Completing the test
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22 General fault criteria (GFC)
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22.1 Testing the underimpedance mode
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22.2 Testing the overcurrent operating mode
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22.3 Testing the phase preference logic
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22.4 Completing the test
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23 High speed binary output logic (HSBO)
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24 Instantaneous nondirectional overcurrent protection(IOC)
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25 Local acceleration logic (ZCLC)
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26 Loss of voltage check (LOV)
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27 Supervision of AC input quantities (DA)
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28 Supervision of mA input quantities (MI)
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29 Multiple command (CM)
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30 Overload supervision (OVLD)
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31 Pole discordance protection (PD)
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32 Pole slip protection (PSP)
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32.1 Measuring the operating characteristics
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32.2 Testing the pole slip functionality
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32.3 Testing the additional functionality
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32.4 Completing the test
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33 Power swing detection (PSD)
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33.1 Testing overview
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33.2 Testing the one-of-three-phase operation
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33.3 Testing the two-of-three-phase operation
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33.4 Testing the tEF timer and functionality
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33.5 Testing the tR1 timer
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33.6 Testing the tR2 timer
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33.7 Testing the block input
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33.8 Completing the test
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34 Pulse counter logic for metering (PC)
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35 Radial feeder protection (PAP)
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36 Setting lockout (HMI)
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37 Scheme communication logic(ZCOM)
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37.1 Testing permissive underreach
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37.2 Testing permissive overreach
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37.3 Testing blocking scheme
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37.4 Checking of unblocking logic
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37.5 Completing the test
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38 Scheme communication logic for residual overcurrentprotection(EFC)
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39 Sensitive directional residual overcurrent protection (WEF1)
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40 Sensitive directional residual power protection (WEF2)
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41 Four parameter setting groups (GRP)
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42 Single command (CD)
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43 Synchrocheck and energizing check(SYN)
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43.1 Testing the phasing function
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43.2 Testing the synchrocheck
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43.2.1
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43.2.2 Testing the voltage difference
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43.2.3 Testing the phase difference
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43.2.4 Testing the frequency difference
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43.2.5 Testing the reference voltage
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43.3 Testing the energizing check
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43.3.1
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43.3.2 Testing the dead line live bus (DLLB)
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43.3.3 Testing the dead bus live line (DBLL)
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43.3.4 Testing both directions (DLLB or DBLL)
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43.3.5 Testing the dead bus dead line (DBDL)
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43.4 Testing the voltage selection
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43.5 Completing the test
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44 Thermal phase overload protection (THOL)
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45 Definite time nondirectional overcurrent protection(TOC)
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46 Time delayed overvoltage protection (TOV)
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47 Time delayed undervoltage protection
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48 Tripping logic (TR)
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49 Two step time delayed directional phase overcurrentprotection(TOC3)
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50 Two step time delayed non-directional phase overcurrentprotection(TOC2)
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51 Low active power protection (LAPP)
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52 Low active and reactiv power protection (LARP)
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53 High active power protection (HAPP)
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54 High active and reactive power protection (HARP)
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55 Sudden change in phase current protection(SCC1)
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56 Sudden change in residual current protection(SCRC)
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57 Sudden change in voltage protection (SCV)
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58 Overvoltage protection (OVP)
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59 Undercurrent protection (UCP)
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60 Phase overcurrent protection (OCP)
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61 Residual overcurrent protection (ROCP)